1. Technical Field of the Invention
The present invention relates to computer systems and, more particularly, to a computer system in which debug information is provided through tag space in a bus transaction.
2. Background Art
Chips in computer systems are becoming increasingly complex. In some cases, validation of the chips in systems in which they are placed takes close to as much time as the original designing of the chips. An important aspect of validation is the observability of internal states. This is often difficult to do because there are a limited number of pins/pads from which to observe internal signals.
A number of bus specifications have been introduced. Versions of the Peripheral Component Interconnect (PCI) Local Bus Specification have been widely used. A PCI Local Bus Specification rev. 2.2 is dated Dec. 18, 1998 by the PCI Special Interest Group (SIG).
More recently, a PCI-X Addendum to the PCI Local Bus Specification rev. 1.0 and 1.0a has been introduced by the PCI SIG. Rev. 1.0a of the PCI-X specification is dated Jul. 24, 2000. Descriptions of the PCI and PCI-X specifications are widely available. For example, T. Shanley, PCI-X System Architecture (MindShare, Inc. 2001) describes the PCI-X specification rev. 1.0.
In the PCI-X specification, a requester makes a transaction request that is completed by a transaction completer. The completer may be on the same or a different bus than the requester. When the requester and completer are on different buses, the buses may be joined through one or more bridges or hubs. When the requester and completer are on the same bus, the completer is the target. When the requester and completer are on different buses joined through a bridge, the bridge is the target.
The target (the completer or bridge) may complete a requested transaction immediately or by means of the PCI-X split transaction protocol. In the split transaction protocol, the target provides a split response to the requester and the target and requester may then proceed to other business. At a later time, the target returns the transaction results in a series of one or more split completion transactions. A sequence is a series of one or more transactions performed to accomplish one overall transfer originally initiated by a requester, such as for example a split request transaction and its corresponding split completion transaction(s). Each transaction associated with a specific sequence uses the same sequence identification (ID), which includes a requester identification (ID) and a tag. The requester ID identifies the requester by providing its bus number, device number, and function number in the transaction's attribute phase. The tag is a 5-bit number that identifies the transaction number from that requester.
In the PCI-X specification, the request includes four phases: address phase, attribute phase, response phase, and data phase(s). A 5-bit tag field is included in bits AD[24]–AD [28] of the attribute phase of the request. The split completion includes four phases: address phase, attribute phase, response phase, and data phase(s). In the split completion address phase, the sequence ID is provided by the completer as an address to identify the original requester. The tag is included in bits AD[24]–AD [28] during the split completion transaction address phase. In the completion attribute phase, bits AD[24]–AD [28] are reserved. A completer ID includes the completer's bus, device, and function numbers and is also provided in the attribute phase. The completer ID is provided for use by testing tools, such as the Agilent Technology PCI bus exerciser.
A PCI Express specification, formerly known as 3GIO (3rd generation input output), is in the process of being defined by the PCI SIG. The PCI Express specification defines the PCI Express bus, signals on the bus, and some details of chips being connected by PCI Express buses. Drafts of the PCI Express specification have been circulated to many companies in the computer industry. The PCI Express specification has some similarities to the PCI and PCI-X specifications, but also many enhancements. For purposes of the present disclosure, it is sufficient to note that the PCI Express specification includes a transaction descriptor for carrying transaction information between a transaction requester and a transaction completer. In some proposed implementations of PCI Express, a tag field is in byte 6 of the request header.
The transaction descriptor contains various fields including a transaction ID which identifies the requester (through bus number, device number, and function number) and a tag which identifies a transaction number from that requester. Different details for the transaction ID field have been proposed. Under different proposals, the tag includes 5 or 8 bits. As can be noticed, the transaction ID field of the PCI Express specification has similarities to the sequence ID of the PCI-X specification. In some implementations, the function number in PCI Express may be a phantom function number. In such a case, some encodings of the 3-bit function number may be used to increase the number of possible transaction numbers. That is, unclaimed function numbers may be used as phantom function numbers that may be used in conjunction with tag bits to increase the number of possible transaction numbers.
It has been proposed that buses using the PCI Express specification be used to join a variety of chips in a computer system including between the north bridge (also called the host bridge, north hub, and memory controller hub) and the south bridge (also called the input/output (I/O) bridge, and I/O controller hub); between the north bridge and a graphics chip (e.g., for what is called the advanced graphics port (AGP)); between the north bridge and additional bridges or switches; between the south bridge and additional bridges or switches; and between additional bridges and switches and chips to which they are connected. There may be multiple bridges and switches cascaded together with PCI Express buses or other buses such as PCI-X buses.